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INTEGRATED CIRCUITS
DATA SHEET
PCF8573 Clock/calendar with serial I/O
Product specification Supersedes data of 1997 March 28 2003 Jan 27
Philips Semiconductors
Product specification
Clock/calendar with serial I/O
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.4 9 9.1 9.2 10 11 12 13 14 15 16 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 16.4 17 18 19 20 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Oscillator Prescaler and time counter Alarm register Comparator Power on/power fail detection Interface level shifters CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge I2C-BUS PROTOCOL Addressing Clock/calendar READ/WRITE cycles LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING Introduction Through-hole mount packages Soldering by dipping or by solder wave Manual soldering Surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of IC packages for wave, reflow and dipping soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
PCF8573
2003 Jan 27
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
1 FEATURES
PCF8573
* Serial input/output I2C-bus interface for minutes, hours, days and months * Additional pulse outputs for seconds and minutes * Alarm register for presetting a time for alarm or remote switching functions * On-chip power fail detector * Separate ground pin for the clock allows easy implementation of battery back-up during supply interruption * Crystal oscillator control (32.768 kHz) * Low power consumption. 2 GENERAL DESCRIPTION The IC incorporates an addressable time counter and an addressable alarm register for minutes, hours, days and months. Three special control/status flags, COMP, POWF and NODA, are also available. Back-up for the clock during supply interruptions is provided by a 1.2 V nickel cadmium battery. The time base is generated from a 32.768 kHz crystal-controlled oscillator.
The PCF8573 is a low threshold, CMOS circuit that functions as a real time clock/calendar. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. 3 QUICK REFERENCE DATA SYMBOL VDD - VSS1 VDD - VSS2 fosc 4 PARAMETER supply voltage, clock (pin 16 to pin 15) supply voltage, I2C-bus (pin 16 to pin 8) crystal oscillator frequency ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8573P PCF8573T DIP16 SO16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 7.5 mm VERSION SOT38-4 SOT162-1 1.1 2.5 - MIN. - - 32.768 TYP. MAX. 6.0 6.0 - V V kHz UNIT
2003 Jan 27
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
5 BLOCK DIAGRAM
FSET SEC MIN VDD
PCF8573
handbook, full pagewidth
11 LS 32.768 kHz OSCO 14 OSCI 13 CT VDD SDA OSCILLATOR PRESCALER 1 : 215 SECONDS COUNTER 1 : 60 LS
10
9
16 1.5 V POWER-ON RESET 15
8 VSS2
4 N 5 MINUTES LS COMPARATOR I2C BUS CONTROL LS TIME COUNTER HOURS DAYS DATE MONTHS
6 7
EXTPF PFIN
SCL
3
COMP
INPUT FILTER
ALARM REGISTER
LS
12
TEST
LS 1 A0 2
LS
LEVEL SHIFTER
PCF8573
MBL804
A1
Fig.1 Block diagram.
6
PINNING DESCRIPTION address input address input comparator output serial data line; I2C-bus serial clock line; I2C-bus enable power fail flag input power fail flag input negative supply 2 (I2C interface) one pulse per minute output one pulse per second output oscillator tuning output test input; connect to VSS2 if not in use oscillator input oscillator input/output negative supply 1 (clock) common positive supply 4 Fig.2 Pinning diagram (DIP16).
VSS2 8
MBL805
SYMBOL PIN A0 A1 COMP SDA SCL EXTPF PFIN VSS2 MIN SEC FSET TEST OSCI OSCO VSS1 VDD 2003 Jan 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
handbook, halfpage
A0 1 A1 2 COMP 3 SDA 4
16 VDD 15 VSS1 14 OSCO 13 OSCI
PCF8573P
SCL 5 EXTPF 6 PFIN 7 12 TEST 11 FSET 10 SEC 9 MIN
Philips Semiconductors
Product specification
Clock/calendar with serial I/O
PCF8573
advance the seconds counter. The carry of the prescaler and the seconds counter are available at the outputs SEC, MIN respectively, and are also readable via the I2C-bus. The mark-to-space ratio of both signals is 1 : 1. The time counter is advanced one count by the falling edge of output signal MIN. A transition from HIGH-to-LOW of output signal SEC triggers MIN to change state. The time counter counts minutes, hours, days and months, and provides a full calendar function which needs to be corrected only once every four years - to allow for leap-year. Cycle lengths are shown in Table 1. 7.3 Alarm register
handbook, halfpage
A0 1 A1 2 COMP 3 SDA 4
16 VDD 15 VSS1 14 OSCO 13 OSCI
PCF8573T
SCL 5 EXTPF 6 PFIN 7 VSS2 8
MBL806
12 TEST 11 FSET 10 SEC 9 MIN
The alarm register is a 24-bit memory. It stores the time-point for the next setting of the status flag COMP. Details of writing and reading of the alarm register are included in the description of the characteristics of the I2C-bus. 7.4 Comparator
Fig.3 Pinning diagram (SO16).
7 7.1
FUNCTIONAL DESCRIPTION Oscillator
The PCF8573 has an integrated crystal-controlled oscillator which provides the timebase for the prescaler. The frequency is determined by a single 32.768 kHz crystal connected between OSCI and OSCO. A trimmer is connected between OSCI and VDD. 7.2 Prescaler and time counter
The prescaler provides a 128 Hz signal at the FSET output for fine adjustment of the crystal oscillator without loading it. The prescaler also generates a pulse once a second to
The comparator compares the contents of the alarm register and the time counter, each with a length of 24 bits. When these contents are equal the flag COMP will be set 4 ms after the falling edge of MIN. This set condition occurs once at the beginning of each minute. This information is latched, but can be cleared by an instruction via the I2C-bus. A clear instruction may be transmitted immediately after the flag is set and will be executed. Flag COMP information is also available at the output COMP. The comparison may be based upon hours and minutes only if the internal flag NODA (no date) is set. Flag NODA can be set and cleared by separate instructions via the I2C-bus, but it is undefined until the first set or clear instruction has been received. Both COMP and NODA flags are readable via the I2C-bus.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
Table 1 Cycle length of the time counter NUMBER OF BITS 7 6 6 COUNTING CYCLE 00 to 59 00 to 23 01 to 28 01 to 30 01 to 31 months Note 5 01 to 12 CARRY FOR FOLLOWING UNIT 59 00 23 00 28 01 or 29 01 30 01 31 01 12 01 2 2
PCF8573
UNIT minutes hours days(1)
CONTENT OF MONTH COUNTER
4, 6, 9, 11 1, 3, 5, 7, 8, 10, 12
1. During February of a leap-year the `Time Counter Days' may be set to 29 by directly writing to it using the `execute address' function. Leap-years must be tracked by the system software. 7.5 Power on/power fail detection The external power fail control operates by absence of the VDD - VSS2 supply. Therefore the input levels applied to PFIN and EXTPF must be within the range VDD - VSS1. A LOW level at PFIN indicates a power fail. POWF is readable via the I2C-bus. A power-on reset for the I2C-bus control is generated on-chip when the supply voltage VDD - VSS2 is less than VTH2. 7.6 Interface level shifters
If the voltage VDD - VSS1 falls below a certain value, the operation of the clock becomes undefined. Therefore a warning signal is required to indicate that faultless operation of the clock is not guaranteed. This information is latched in a flag called POWF (Power Fail) and remains latched after restoration of the correct supply voltage until a write sequence with EXECUTE ADDRESS has been received. The flag POWF can be set by an internally generated power fail level-discriminator signal for applications with (VDD - VSS1) greater than VTH1, or by an externally generated power fail signal for applications with (VDD - VSS1) less than VTH1. The external signal must be applied to the input PFIN. The input stage operates with signals of slow rise and fall times. Internally or externally controlled POWF can be selected by input EXTPF as shown in Table 2. Table 2 Power fail selection PFIN(1) 0 1 0 1 test mode power fail is sensed externally no power fail sensed FUNCTION power fail is sensed internally
EXTPF(1) 0 0 1 1 Note
The level shifters adjust the 5 V operating voltage (VDD - VSS2) of the microcontroller to the internal supply voltage (VDD - VSS1) of the clock/calendar. The oscillator and counter are not influenced by the VDD - VSS2 supply voltage. If the voltage VDD - VSS2 is absent (VDD = VSS2), the output signal of the level shifter is HIGH because VDD is the common node of the VDD - VSS2 and VDD - VSS1 supplies. Because the level shifters invert the input signals, the internal circuit behaves as if a LOW signal is present on the inputs. FSET, SEC, MIN and COMP are CMOS push-pull output stages. The driving capability of these outputs is lost when the supply voltage VDD - VSS2 = 0.
1. 0 = VSS1 (LOW); 1 = VDD (HIGH).
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
8 CHARACTERISTICS OF THE I2C-BUS
PCF8573
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer
See Fig.4. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.4 Bit transfer.
8.2
Start and stop conditions
Refer to Fig.5. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.5 Definition of start and stop conditions.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
8.3 System configuration
PCF8573
Refer to Fig.6. A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'.
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
MBA605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig.6 System configuration.
8.4
Acknowledge
See Fig.7. The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition, see Figs. 10 and 11.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.7 Acknowledgment on the I2C-bus.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
9 9.1 I2C-BUS PROTOCOL Addressing
PCF8573
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.8. Bits A0 and A1 correspond to the two hardware address pins A0 and A1. Connecting these to VDD or VSS allows the device to have 1 of 4 different addresses.
handbook, halfpage
msb
lsb
1
1
0
1
0
A1
A0
R/W
MBL807
Fig.8 Slave address.
9.2 The
Clock/calendar READ/WRITE cycles I2C-bus configuration for different clock/calendar READ and WRITE cycles is shown in Figs 9, 10 and 11.
The write cycle is used to set the time counter, the alarm register and the flags. The transmission of the clock/calendar address is followed by the MODE-POINTER-word which contains a CONTROL-nibble (Table 3) and an ADDRESS-nibble (Table 4). The ADDRESS-nibble is valid only if the preceding CONTROL-nibble is set to EXECUTE ADDRESS. The third transmitted word contains the data to be written into the time counter or alarm register.
handbook, full pagewidth
acknowledge from slave R/W S CLOCK/CALENDAR 0A ADDRESS
acknowledge from slave
msb MODE POINTER
acknowledge from slave
lsb
A
DATA
A
P
n bytes (n = 0, 1, 2, ...)
auto increment of B1, B0 0 C2 C1 C0 0 B2 B1 B0
MBL808
Fig.9 Master transmitter transmits to clock/calendar slave receiver.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
PCF8573
handbook, full pagewidth
acknowledge from slave R/W
acknowledge from slave
acknowledge from slave R/W msb
acknowledge from master lsb DATA (n - 1) bytes A msb
S
CLOCK/CALENDAR 0A ADDRESS
MODE POINTER
A
S
CLOCK/CALENDAR 1A ADDRESS
at this moment master transmitter becomes master receiver, and CLOCK/CALENDAR becomes slave transmitter
auto increment of B1, B0
no acknowledge (1) lsb DATA nth byte auto increment of B1, B0
MBL809
1
P
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
Fig.10 Master transmitter reads clock/calendar after setting mode pointer.
handbook, halfpage
acknowledge from slave R/W
MSB
acknowledge from master (1)
LSB
S
CLOCK/CALENDAR ADDRESS
1A
DATA
A
P
n bytes
auto increment of B1, B0
MBL810
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
Fig.11 Master reads clock/calendar immediately after first byte.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
Table 3 BIT 8 0 0 0 0 0 0 0 Note MODE-POINTER-word, CONTROL-nibble (bits 8, 7, 6 and 5) C2 0 0 0 0 1 1 1 C1 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 execute address read control/status flags FUNCTION
PCF8573
reset prescaler, including seconds counter; without carry for minute counter time adjust, with carry for minute counter (note 1) reset NODA flag set NODA flag reset COMP flag
1. If the seconds counter is below 30 there is no carry. This causes a time adjustment of max. -30 s. From the count 30 there is a carry which adjusts the time by max. +30 s. Table 4 BIT 4 0 0 0 0 0 0 0 0 MODE-POINTER-word, ADDRESS-nibble (bits 4, 3, 2 and 1) B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 time counter hours time counter minutes time counter days time counter months alarm register hours alarm register minutes alarm register days alarm register months ADDRESSED TO:
At the end of each data word the address bits B1, B0 will be incremented automatically provided the preceding CONTROL-nibble is set to EXECUTE ADDRESS. There is no carry to B2. Table 5 shows the placement of the BCD upper and lower digits in the DATA byte for writing into the addressed part of the time counter and alarm register respectively. Table 6 shows the acknowledgement response of the clock calendar as a slave receiver. Table 5 MSB UPPER DIGIT UD X X X X Note 1. `X' is the don't care bit; `D' is the data bit. UC X D X X UB D D D X UA D D D D LD D D D D Placement of BCD digits in the DATA byte; note 1 DATA LOWER DIGIT LC D D D D LB D D D D LA D D D D hours minutes days months LSB ADDRESSED TO:
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
PCF8573
Acknowledgement response of the PCF8573 as slave-receiver is shown in Table 6. Note that data is only associated with the `execute address' function where C0, C1, C2 = 0, 0, 0. Table 6 Slave receiver acknowledgement; note 1 MODE POINTER BIT 8 0 0 0 0 0 0 0 0 0 1 Note 1. `X' is `don't care'. To read the addressed part of the time counter and alarm register, plus information from specified control/status flags, the BCD digits in the DATA byte are organized as shown in Table 7. The status of the CONTROL-nibble of the MODE-POINTER-WORD (C2, C1, C0) remains unchanged until re-written. Table 7 MSB UPPER DIGIT UD 0 0 0 0 0 Note 1. `D' is the data bit; `m' = minutes; `s' = seconds. UC 0 D 0 0 0 UB D D D 0 0 UA D D D D m LD D D D D s Organization of the BCD digits in the DATA byte; note 1 DATA LOWER DIGIT LC D D D D NODA LB D D D D COMP LA D D D D POWF hours minutes days months control/status flags LSB ADDRESSED TO: C2 0 0 0 0 0 1 1 1 1 X C1 0 0 0 1 1 0 0 1 1 X C0 0 0 1 0 1 0 1 0 1 X BIT 4 0 1 X X X X X X X X B2 X X X X X X X X X X B1 X X X X X X X X X X B0 X X X X X X X X X X ACKNOWLEDGE ON BYTE: ADDRESS yes yes yes yes yes yes yes yes yes yes MODE POINTER yes no yes yes yes yes yes yes no no DATA yes no no no no no no no no no
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD - VSS1 VDD - VSS2 Vl PARAMETER supply voltage (pin 16 to pin 15) supply voltage (pin 16 to pin 8) input voltage pins 4 and 5 (with input impedance of minimum 500 ) VSS2 - 0.8 pins 6, 7, 13 and 14 any other pin Il IO Ptot PO Tamb Tstg DC input current DC output current total power dissipation per package power dissipation per output operating ambient temperature storage temperature VSS1 - 0.6 VSS2 - 0.6 - - - - -40 -55 VDD + 0.8 VDD + 0.6 VDD + 0.6 10 10 200 100 +85 +125 -0.3 -0.3 MIN. +8.0 +8.0
PCF8573
MAX. V V V V V
UNIT
mA mA mW mW C C
11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
12 DC CHARACTERISTICS VSS2 = 0 V; Tamb = -40 to + 85 C unless otherwise specified. Typical values at Tamb = 25 C. SYMBOL Supply VDD - VSS2 supply voltage (I2C interface) VDD - VSS1 supply voltage (clock) ISS1 supply current at VSS1 (pin 15) supply current at VSS2 (pin 8) LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = VSS2 or VDD tHD;DAT 300 ns see Fig.12 VDD - VSS1 = 1.5 V VDD - VSS1 = 5 V ISS2 VDD - VSS2 = 5 V; IO = 0 all outputs - - - -3 -12 - -10 -50 -50 2.5 1.1 5.0 1.5 6.0 PARAMETER CONDITIONS MIN. TYP.
PCF8573
MAX.
UNIT
V V A A A
VDD - VSS2
Input SCL, input/output SDA VIL VIH ILI Ci VIL VIH ILI VIL VIH ILI - 0.7VDD -1 - - 0.7VDD VI = VSS2 or VDD -250 0 VI = VSS1 to VDD VI = VSS1 to VDD; Tamb = 25 C Output SDA (N-channel open-drain) VOL ILI LOW level output voltage input leakage current output ON; IO = 3 mA; VDD - VSS2 = 2.5 to 6 V VDD - VSS2 = 6 V; VO = 6 V VDD - VSS2 = 2.5 V; IO = 0.3 mA VDD - VSS2 = 4 to 6 V; IO = 1.6 mA VOH HIGH level output voltage VDD - VSS2 = 2.5 V; IO = -0.1 mA VDD - VSS2 = 4 to 6 V; IO = -0.5 mA - -1.0 - - 0.4 +1.0 V A -1.0 -0.1 - - - - - - - - - - 0.3VDD - +1 7 V V A pF
Inputs A0, A1, TEST LOW level input voltage HIGH level input voltage input leakage current 0.2VDD - +250 V V nA
Inputs EXTPF, PFIN LOW level input voltage HIGH level input voltage input leakage current 0.2VDD - VSS1 V - +1.0 +0.1 V A A 0.7VDD - VSS1 -
Output SEC, MIN, COMP, FSET (normal buffer outputs) VOL LOW level output voltage - - VDD - 0.4 VDD - 0.4 - - - - 0.4 0.4 - - V V V V
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
PCF8573
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Internal threshold voltages VTH1 VTH2 power failure detection Power-on reset 1 1.5 1.2 2.0 1.4 2.5 V V
handbook, halfpage
-12
MGL072
ISS1 (A) -8
-4
0 0 2 4 VDD-VSS1 (V) 6
Fig.12 Typical supply current (ISS1) as a function of clock supply voltage (VDD - VSS1) at Tamb = -40 to +85 C.
2003 Jan 27
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
13 AC CHARACTERISTICS VSS2 = 0 V; Tamb = -40 to +85 C unless otherwise specified. Typical values at Tamb = +25 C. SYMBOL PARAMETER CONDITIONS - - - - - - MIN. - - - - - - TYP.
PCF8573
MAX.
UNIT s s s s s s
Rise and fall times of input signals tr rise time input EXTPF input PFIN all other inputs (levels between VIL and VIH) tf fall time input EXTPF input PFIN all other inputs (levels between VIL and VIH) Oscillator Cosc Rf fosc integrated oscillator capacitance oscillator feedback resistance oscillator stability (VDD - VSS1) = 100 mV; Tamb = 25 C; (VDD - VSS1) = 1.55 V - - - 40 3 2x 10-7 - - - pF M 1 1 1 0.3
Quartz crystal parameters (f = 32.768 kHz) Rs CL CT series resistance parallel load capacitance trimmer capacitance - - 5 - - 4.7 4.7 4.0 4.7 4.0 - - 250 0 - 4.0 - 10 - - - - - - - - - - - - - - 40 - 25 k pF pF
I2C-bus timing (see Fig.13; notes 1 and 2) fSCL tSP tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO Notes 1. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and VIH with an input voltage swing of VSS to VDD. 2. A detailed description of the I2C-bus specification, with applications, is given in brochure "The I2C-bus and how to use it". This brochure may be ordered using the code 9398 393 40011. SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid STOP condition set-up time 100 100 - - - - - 1.0 0.3 - - 3.4 - kHz ns s s s s s s s ns ns s s
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
PCF8573
handbook, full pagewidth
PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 LSB (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (P)
t SU;STA
t LOW
t HIGH
1 / f SCL
SCL
t
BUF
tr
tf
SDA
t HD;STA
t SU;DAT
t
HD;DAT
t VD;DAT
MBD820
t SU;STO
Fig.13 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
14 APPLICATION INFORMATION
handbook, full pagewidth
PCF8573
+5 V R: pull-up resistor R VDD R
PCF8570
128 x 8 BIT STATIC CMOS RAM VSS 32.768 kHz CT R1
SDA
MASTER DEVICE SCL MICROCONTROLLER
PCF8577
EXTPF VDD PFIN R2 R3 A0 OSCO OSCI SDA SCL A1 VSS2 TEST VSS1 1.2 V (NiCa) Rch: resistor for permanent charging I2C bus
PCF8573
64 LCD SEGMENT DRIVER
8 DIGIT LCD
MBL811
detection circuit with very high impedance
Fig.14 Application example of the PCF8573 clock/calendar with battery backup.
handbook, full pagewidth
+5 V
R
R
1.5 V
C SDA SCL
SCL SDA VDD
SCL SDA VDD A0 OSCI A1
CT
SCL SDA VDD
MASTER MICROCONTROLLER
PCF8573 PCF8571
OSCO VSS1 VSS
MBL812
TEST PFIN EXTPF VSS2
VSS
Fig.15 Application example of the PCF8573 with common VSS1 and VSS2 supply.
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
15 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil)
PCF8573
SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.030
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
2003 Jan 27
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Philips Semiconductors
Product specification
Clock/calendar with serial I/O
PCF8573
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
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Product specification
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16 SOLDERING 16.1 Introduction
PCF8573
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 16.3.2 WAVE SOLDERING
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 16.2.1 Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3.3 MANUAL SOLDERING
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 16.3 16.3.1 Surface mount packages REFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 21
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Product specification
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16.4 Suitability of IC packages for wave, reflow and dipping soldering methods MOUNTING PACKAGE(1) suitable(3) not suitable(4) suitable not recommended(5)(6) not recommended(7)
PCF8573
SOLDERING METHOD WAVE REFLOW(2) DIPPING - suitable suitable suitable suitable suitable suitable - - - - -
Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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17 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
PCF8573
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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20 PURCHASE OF PHILIPS I2C COMPONENTS
PCF8573
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Product specification
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NOTES
PCF8573
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Philips Semiconductors
Product specification
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NOTES
PCF8573
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Product specification
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NOTES
PCF8573
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/04/pp28
Date of release: 2003
Jan 27
Document order number:
9397 750 10463

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